Die seal ring structures (also referred to as ‘chip seal rings’ or ‘seal rings’) are commonly used around the periphery of integrated circuits (ICs) in order to protect the circuit components from mechanical damage both during assembly and in operation. The main risk of mechanical damage in assembly arises from cracks in the dielectric layers which may occur when a processed wafer is diced into individual die (e.g. using a wafer saw). These cracks in the dielectric layers may then propagate further into the die if it is thermally cycled (e.g. during assembly or during operation). Other damage, such as chipping, may also occur when the wafer is diced. In operation, the die seal ring protects the chip edge from the diffusion of moisture and mobile ions (also referred to as ‘ionic contamination’) into the die. If moisture ingress is not stopped, the moisture can result in an increase in the dielectric constant of oxides and reduce the reliability of the die through various mechanisms. The ingress of mobile ions, if allowed, can also affect the reliability and performance of the IC.
FIG. 1a shows a schematic diagram of a die 100 which includes a die seal ring 101 which surrounds the circuitry 102 of the IC. The die seal ring structure 101 comprises a continuous barrier of metals formed by all the conductive layers within the die, including contacts, metals and vias. FIG. 1a also shows a region 103 inside the die seal ring, which may be referred to as a ‘keep-out zone’, which is not occupied by any circuitry, such that the die seal ring 101 and the circuitry are always separated by a certain distance (i.e. the width of the keep-out zone).
The die seal ring is usually tied to the substrate of the die (or to the ground of the IC via the substrate) to prevent the build up of electrical charge and to prevent it from forming an inductor around the IC.
The continuous seal ring structure 101 shown in FIG. 1a, however, can be detrimental to the performance of the IC as the seal ring spreads unwanted signals across the die. Such signals may be picked up from the substrate or by inductive coupling, for example, where the seal ring runs close to a noisy or high power circuit and can cause interference in voltage references, voltage-controlled oscillators, low noise amplifiers and other sensitive analogue circuits. Examples of interferers include digital switching noise, power amplifiers and switched DC/DC converters.
Although the schematic diagram of die 100 in FIG. 1a shows a single die seal ring 101, in some examples, the die seal ring structure may comprise independent inner and outer rings or tracks. In such a configuration, the outer track may predominantly be intended to prevent the propagation of cracks which may formed during dicing of the wafer into individual die, whilst the inner track (which is usually wider than the outer track) provides a hermetic seal against ingress of moisture and mobile ions.
A solution that has been proposed in order to reduce the spread of noise by the die seal ring around the perimeter of the die involves the introduction of breaks 112 and 124 into the die seal ring 101 and 121, as shown in the schematic diagram in FIGS. 1b and 1c. In a first example, as shown in FIG. 1b, the die seal ring 101 around the periphery of the die 110 includes a break 112. In a second example, as shown in FIG. 1c, which shows an enlarged portion of a die seal ring 121, the die seal ring comprises an outer track 122 and an inner track 123 and a break 124 is introduced into both tracks. Other solutions involve designing the circuits on the IC to tolerate the noise coupled by the seal ring or increasing the width of the keep-out zone to reduce coupling between the die seal ring and the circuitry. Increasing the width of the keep-out zone is, however, undesirable as it either results in a larger die or reduces the available area for circuitry.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known die seal rings and die seal ring designs.